As the semiconductor industry introduces new generations of integrated circuits (IC's) having higher performance and greater functionality, the density of the elements that form the integrated circuits is increased, and the dimensions, sizes and spacing between the individual components or elements are reduced. While in the past such reductions were limited only by the ability to define the structures photo-lithographically, device geometries having even smaller dimensions created new limiting factors. For example, for any two adjacent conductive paths, as the distance between conductors decreases, the resulting capacitance (a function of the dielectric constant (k) of the insulating material divided by the distance between conductive paths) increases. This increased capacitance results in increased capacitive coupling between the conductors, increased power consumption, and an increase in the resistive-capacitive (RC) time constant. Therefore, the continual improvement in semiconductor IC performance and functionality is dependent upon developing materials that form a dielectric film with a lower dielectric constant (k value) than that of the most commonly used material, silicon oxide, thus resulting in reduced capacitance. As the dimensions of these devices get smaller and smaller, significant reductions in capacitance into the so-called “ultra low k” regime is required.
New materials with low dielectric constants (known in the art as “low-k dielectrics”) are being investigated for their use as insulators in semiconductor chip designs. A low dielectric constant material aids in enabling further reduction in the integrated circuit feature dimensions. The substance with the lowest dielectric constant is air (k=1.0). Therefore, porous dielectrics are very promising candidates since they have the potential to provide very low dielectric constants.
However, porous dielectrics are mechanically weak by nature. Weak dielectrics would fail in the chemical mechanical polish (CMP) process employed to planarize the wafer surface during chip manufacturing. The mechanical properties of a porous dielectric are functions of the porosity of the dielectric. Naturally, higher porosity results in lower dielectric constant but also poorer mechanical properties. As a result, delamination may occur between the porous low-k dielectric and a superjacent or subjacent metal when a chemical mechanical polish is performed, due to the mechanical stress applied by the CMP. When integrated circuits become smaller, materials with lower k, hence lower mechanical strength, are expected to be used, resulting in more severe problems.
To overcome the problems caused by weak mechanical properties of low-k dielectrics, stress free polishing (SFP) is gradually replacing CMP, especially in damascene processes that involve copper and low-k dielectrics. SFP can be completely stress free, thus it is suitable for working with dielectrics having very low mechanical strength.
SFP suffers drawbacks, however. SFP does not have good planarization ability, thus very complex dummy patterns are typically required in order to form planar surfaces. FIGS. 1 and 2 illustrate a conventional damascene process, wherein electro-chemical plating is combined with stress free polishing. FIG. 1 illustrates openings 1001 and 1002 formed in a low-k dielectric layer 102. Openings 1001 are closely spaced and have small dimensions. Opening 1002 has a relatively greater (wider) dimension. A copper or a copper alloy is filled into the openings 1001 and 1002 by electro-chemical plating, forming a copper layer 103. As a result of the patterned surface of the dielectric layer 102, a hump 104 is formed over the dense and narrow openings 1001, and a recess 106 is formed over the opening 1002.
An (stress free) electro-polishing is then performed to remove excessive copper, as shown in FIG. 2. The resulting structure has a topographic surface. While copper 108 in the opening 1002 is typically recessed, a hump 110 may be formed over the openings 1001 and interconnects the metal features in openings 1001, causing integrated circuit failure. This potential problem significantly limits the usage of stress free polishing in the manufacture of integrated circuits. Therefore, a method that maximizes the benefit of stress free polishing without causing a non-planar surface is needed.